module test_alu ();

reg CLK;
reg [7:0] A, B;
reg CBi;
reg [3:0] FUNC;
reg nALURESET;
wire CBo, OV, ZR;
wire [7:0] Y;

initial
begin
	CLK = 0; /*Init*/
	A = 8'h00;
	B = 8'h00;
	CBi = 1'b0;
	FUNC = 4'b1100; /*Choose function*/
	nALURESET = 0; #10; /*Reset ALU*/
	nALURESET = 1;
	repeat (2)
	begin
		repeat (256)
		begin
			repeat (256)
			begin
				#5;
				CLK = 1;
				#5;
				CLK = 0;
				B = B + 1;
			end
			A = A + 1;
		end
		CBi = CBi + 1;
	end
	$finish;
end

alu DUT (CLK, A, B, CBi, FUNC, nALURESET, CBo, OV, ZR, Y);

endmodule